The design of digital electronic circuits requires verification of the design before fabrication, and also ability to troubleshoot or characterize a hardware electronic circuit after manufacturing. In both cases, a Logic Analyzer is an essential tool, from a semiconductor chip level all the way to a board and system level. Emulation systems are one type of a verification system that can be used to verify the electronic circuit design before fabrication, and a logic analyzer is typically integrated into high end emulation systems. After fabrication, a stand-alone logic analyzer, or a digital oscilloscope can be used to troubleshoot design or manufacturing problems at the board or system level. The boundaries between advanced digital oscilloscopes and logic analyzers have become blurred, but they are all based on the same underlying principle of capturing multiple samples of signal values along the time axis and presenting them later to the user after some processing. The data is displayed as either waveforms or in textual format. The captured data can also be processed by other software tools, typically running on an external workstation, for various purposes such as power analysis, bus protocol compliance, etc.
One type of verification system for a Device Under Test (DUT) is a hardware emulation system that aims to increase verification productivity, speed up time-to-market, and deliver greater confidence in the final system on chip product. A hardware emulation system is in communication with a workstation. The DUT is the term given to the part of the design that is being emulated by the emulation system.
A conventional logic analyzer is usually integrated into the hardware emulation system. The logic analyzer is an electronic instrument that is used to capture and display data signals of the DUT that carry digital information. Generally, the logic analyzer captures the data signals that are too fast to be observed by a circuit designer. The circuit designer observes the data signals captured by the logic analyzer to effectively analyze the DUT and use the analysis to take preemptive actions or debug. As a result, the logic analyzer can provide visibility of the DUT undergoing emulation.
The logic analyzer includes a trace buffer, which is in communication with the signals in the DUT. The trace buffer stores the captured data signals from the elements of the DUT undergoing emulation. Control circuitry communicates with the signals in the DUT and generates logic analyzer clock signals that clock the data into the trace buffer. The control circuitry also generates trigger signals when predetermined sequences of signal values, as defined by the circuit designer, occur in the DUT.
The conventional logic analyzer integrated in the hardware emulation system can be programmable to capture and store the data signals in the trace buffer as specified by the circuit designer. The data signals can include a preset amount of data samples having values of the DUT signals that occur before a defined trigger point. The trigger point is typically defined as a condition based on signal values in the DUT or a sequence of such conditions. In other words, the conventional logic analyzer is programmable to capture the data history preceding the trigger point to the trace buffer. The data signals stored by the logic analyzer may then be transferred to a computer for further analysis.
FIG. 1A illustrates a block diagram of a conventional logic analyzer system of an emulation system 100 in an electronic design automation system for verifying that a logic design conforms to its specification before the logic design is manufactured as integrated circuits (ICs). The logic designs may be described using various languages, such as hardware description languages (HDLs) or other more abstract languages. Functional verification is performed using an emulation process. In the emulation process, the logic design is mapped into a hardware emulator to provide a design under test (DUT) 102.
The logic analyzer system receives a plurality of data signals from the DUT 102. The logic analyzer system is programmable to select a plurality of data signals to be sampled. Selected signals from the DUT 102 are probed and sent to a trigger detection circuit 104 and a trace buffer 106 of the logic analyzer. The data signals received from the DUT 102 are then written into the trace buffer 106 as a circular buffer. In each clock cycle, one data sample of the data signals is written into the trace buffer 106 at a given trace address generated by an address counter 108. After the data sample is written into the given trace address, the address counter 108 advances to point to a next trace address in the trace buffer 106 where the data samples are written. When the address counter 108 reaches a highest available trace address of the trace buffer 106, the address counter 108 continues from a starting point of the trace address, thereby overwriting the old data samples stored in the trace buffer 106.
This process continues until the trigger detection circuit 104 detects a trigger pattern from the captured data signals. The trigger detection circuit 104 is programmable to set a trigger condition and to detect if the captured data signals satisfy the trigger condition. If the trigger condition is satisfied, the trigger detection circuit 104 generates a trigger signal. Upon the generation of the trigger signal, the trigger signal is transmitted to the address counter 108, which causes the address counter 108 to stop counting, and thereby stops capturing the data samples into the trace buffer 106. The data samples stored in the trace buffer 106 may then be transferred to a processing unit 110, which interprets the data samples and displays it on a screen or saves it for further processing.
While transferring the data samples from the trace buffer 106 to the processing unit 110, the logic analyzer cannot continue to capture new data samples in situations when the DUT in the emulation system is connected to a target system whose clock signal cannot be stopped. Otherwise, the logic analyzer may overwrite the data samples in the trace buffer 106 that were already captured, but not yet transferred from the trace buffer 106 to the processing unit 110. Thus, in the conventional logic analyzer of the emulation system 100, the DUT clock signal has to be stopped for the purpose of reading the data samples from the trace buffer 106. The conventional logic analyzer, therefore, cannot capture data history for more than one trigger event when the target system connected to the DUT is a dynamic electronic circuit whose clocks cannot be stopped.
FIG. 1B illustrates a diagram showing the contents of the trace buffer 106 of the conventional logic analyzer system of the emulation system 100. The trace buffer 106 has a total capacity of 4096 addresses. In one example, the data samples obtained from the DUT 102 are written into the trace buffer 106. In each clock cycle, one data sample is written into the trace buffer 106 at a given trace address generated by the address counter 108. The trigger detection circuit 104 detects the trigger pattern from the captured data signals. The trigger detection circuit 104 is further programmable to set the trigger condition and detect if the received data signals satisfy the trigger condition. In the illustrated example, assuming that the trigger condition is satisfied at a trace address 300, then the trigger detection circuit 104 generates the trigger signal. Upon the generation of the trigger signal, the trigger signal is transmitted to the address counter 108 which causes the address counter 108 to stop counting, and thereby stops capturing the data samples into the trace buffer 106. The data samples in the trace buffer 106 are now divided into two blocks, where the oldest captured data samples are stored in trace addresses from 301 to 4095, followed by trace addresses from 0 to 300. Thus, the trace buffer 106 of the conventional logic analyzer of the emulation system 100 is only able to record history of the data signals that occurred before the single trigger point as depicted in FIG. 1C.
The drawback of the above techniques employed by the conventional logic analyzer is that in some cases the conditions for the trigger points may occur several times while running the test, while only one of those trigger points has useful data history that the designer needs. If in such situation it is impossible to determine whether the data history that was captured before the trigger point is useful and that determination can be done only at a later point in time during the test (possibly many million of cycles later), then there is no way to know which trigger point should really stop the clocks for the purpose of reading the data history.
Therefore, there is a need in the art for methods and systems that address the above mentioned drawbacks of the techniques employed by the conventional logic analyzer of the emulation system that can capture data sample history preceding one trigger point only before the logic analyzer needs to stop capturing new data samples in order to transfer the capture data samples to a processing unit for further analysis.